1 features ? 8-bit bi-directional i/o port individual pull-up resistors data and low-order address port for external data sram description the AVRPORTA module is an 8-bit, general purpose i/o port. it is also used to output the low-order address byte and to transfer data when accessing external data memory. specific peripheral information the AVRPORTA peripheral is approximately 260 gates. it is designed and described in this datasheet to perform functionally identical to port a in the avr ? atmega103 datasheet (literature #0945b). any differences will be listed in the section named ? modifications to standard product. ? the peripheral was designed to function like the standard product to enable smoother transition for customers who began development and production with an avr standard product and now wish to integrate their design into an asic. if the configuration of AVRPORTA does not satisfy customer requirements, it can be modified to different specifications. this datasheet is described with a tri-state databus configuration, which is the same configuration as the avr standard products. if desired, the AVRPORTA peripheral can be provided in a split databus configuration. figure 1. physical connections cp1 cp2 ireset sre ale adr[5:0] iore iowe dbus[7:0] avr porta clock and control i/o bus instruction bus port connections topada[7:0] padena[7:0] plupba[7:0] frompada[7:0] xadr2ad xadout xreb xadr[7:0] ramdi[7:0] gate array/ embedded array asic macrocell AVRPORTA preliminary rev. 1275a ? 07/00
AVRPORTA 2 table 1. AVRPORTA signal descriptions connection name description direction description avr control cp1 system clock (phase 1) input external sram data is latched on cp1 positive edge. cp2 system clock (phase 2) input any port a register contents are updated only on cp2 positive edge. ireset internal reset input all port a registers are reset to zero by reading dbus, which is driven low by the avr. adr[5:0] i/o registers address bus input valid only when accompanied by iore or iowe. iore i/o registers read enable input enables a read from the i/o location addressed by adr[5:0]. iowe i/o registers write enable input enables a write to the i/o location addressed by adr[5:0]. dbus[7:0] data bus input/output system data bus ? can also be implemented as a split data bus. i/o port ale address latch enable output latches low-order address byte into port a when asserted (first access cycle). data is latched into porta when de-asserted (second access cycle). sre external sram enable input when asserted, the alternate pin functions of ad0-7 on port a are activated. topada[7:0] input to i/o pad output this 8-bit intermediate bus connects to the port a i/o pads at the top level of the architecture. padena[7:0] output enable to i/o pad output this 8-bit bus is the internal logic that sets up each individual port line to an input or an output. plupba[7:0] pull-up input output this 8-bit bus is the internal logic that controls the mos pull-up resistor on each individual port line. frompada[7:0] directly from i/o pad input this 8-bit intermediate bus connects to the port a i/o pads at the top level of the architecture. xadr2ad external address enable input this signal, when asserted and accompanied by sre, drives the low- order external sram address byte onto topada[7:0]. xadout external address output enable input this signal, when asserted and accompanied by sre, drives padena[7:0] high, setting port a up as an output port. xreb external sram read enable input this signal, when de-asserted and accompanied by sre, drives frompada[7:0] onto dbus[7:0], enabling a read of port a. instruction bus xadr[7:0] external sram address input low-order address byte of external sram. this is an input to the AVRPORTA module because the address is sent back out to the port a i/o pads via topada[7:0]. ramdi[7:0] external sram data input data byte to/from external sram. this is an input to the AVRPORTA module because the address is sent back out to the port a i/o pads via topada[7:0].
AVRPORTA 3 recommendations i/o memory map in an asic design, the AVRPORTA may be placed anywhere within the i/o memory map. however, it is recommended that the addressing scheme in table 2 be followed due to the following reasons. 1. any software that exists for an avr standard prod- uct will be ported more easily to the new avr- based asic. 2. new software development using avr studio ? can be done using the built-in i/o port a peripheral window. if AVRPORTA is relocated within the mem- ory map, all port a activity within avr studio may only be observed via the i/o section of the new memory view window . interrupt priority there are no interrupts associated with this implementation of AVRPORTA. i/o-ports port a port a is an 8-bit, bi-directional i/o port with internal pull- ups. three data memory address locations are allocated for port a, one each for the data register ? porta, $1b($3b), data direction register ? ddra, $1a($3a) and the port a input pins ? pina, $19($39). the port a input pins address is read only, while the data register and the data direction register are read/write. all port pins have individually selectable pull-up resistors. the port a output buffers can sink 40 ma and thus drive led displays directly. when pins pa0 to pa7 are used as inputs and are externally pulled low, they will source cur- rent if the internal pull-up resistors are activated. the port a pins have alternate functions related to the optional external data sram. port a can be configured to be the multiplexed low-order address/data bus during accesses to the external data memory. when port a is set to the alternate function by the sre ? external sram enable ? bit in the mcucr ? mcu control register, the alternate settings override the data direction register. the only functional difference between the AVRPORTA peripheral and port a in the avr atmega103 is the logic associated with the sre bit in the mcu control register. if the asic is designed with the external sram high-order address residing on a multi-function i/o port, the assertion of sre disables the port from functioning as digital i/o. however, this will not be the case if the customer elects to design the asic with a dedicated external sram address bus. modifications to standard product table 2. recommended placement of AVRPORTA into i/o memory map address name description $1b porta port a data register $1a ddra port a data direction register $19 pina port a input pins
AVRPORTA 4 the port a data register - porta the port a data direction register - ddra the port a input pins address - pina the port a input pins address ? pina ? is not a register, and this address enables access to the physical value on each port a pin. when reading porta the porta data latch is read, and when reading pina, the logical values present on the pins are read. porta as general digital i/o all eight bits in port a are equal when used as digital i/o pins. pan, general i/o pin: the ddan bit in the ddra register selects the direction of this pin, if ddan is set (one), pan is configured as an output pin. if ddan is cleared (zero), pan is configured as an input pin. if portan is set (one) when the pin configured as an input pin, the mos pull up resistor is activated. to switch the pull up resistor off, portan has to be cleared (zero) or the pin has to be configured as an output pin. note: n: 7, 6...0, pin number bit 76543210 $1b ($3b) porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 porta read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 $1a ($3a) dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 ddra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 $19 ($39) pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 pina read/writerrrrrrrr initial value hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z table 3. ddan effects on port a pins ddan portan i/o pull up comment 0 0 input no tri-state (hi-z) 0 1 input yes pan will source current if ext. pulled low. 1 0 output no push-pull zero output 1 1 output no push-pull one output
AVRPORTA 5 port a schematics note that all port pins are synchronized. the synchronization latch is, however, not shown in the figure. figure 2. porta schematic diagrams (pins pa0 - pa7)
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